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| A '''numerically controlled oscillator''' ('''NCO''') is a digital [[signal generator]] which creates a [[Synchronous circuit|synchronous]] (i.e. clocked), discrete-time, discrete-valued representation of a [[waveform]], usually [[sinusoidal]].<ref name="IEEE">Jane Radatz, The IEEE Standard Dictionary of Electrical and Electronics Terms, IEEE Standards Office, New York, NY, 1997</ref> NCOs are often used in conjunction with a [[digital-to-analog converter]] (DAC) at the output to create a [[direct digital synthesizer]] (DDS).{{#tag:ref|While some authors use the terms DDS and NCO interchangeably,<ref name="latticeSC" /> by convention an NCO refers to the digital (i.e. the discrete-time, discrete amplitude) portion of a DDS<ref name="IEEE"/>}}
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| Numerically controlled oscillators offer several advantages over other types of oscillators in terms of agility, accuracy, stability and reliability.<ref name="latticeSC">{{cite web|title=Numerically Controlled Oscillator
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| |url=http://www.latticesemi.com/products/intellectualproperty/ipcores/numericallycontrolledosci/index.cfm
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| |publisher=Lattice Semiconductor Corporation|year=2009}}</ref> NCOs are used in many communications systems including digital up/down converters used in 3G wireless and software radio systems, digital PLLs, radar systems, drivers for optical or acoustic transmissions, and multilevel [[Frequency-shift keying|FSK]]/[[Phase-shift keying|PSK]] modulators/demodulators.<ref name="latticeSC"/>
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| ==Operation==
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| An NCO generally consists of two parts:
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| *A ''phase accumulator'' (PA), which adds to the value held at its output a frequency control value at each clock sample.
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| *A ''phase-to-amplitude converter'' (PAC), which uses the phase accumulator output word (phase word) usually as an index into a waveform [[look-up table]] (LUT) to provide a corresponding amplitude sample. Sometimes [[linear interpolation|interpolation]] is used with the look-up table to provide better accuracy and reduce phase error noise. Other methods of converting phase to amplitude, including mathematical algorithms such as [[power series]] can be used, particularly in a software NCO.
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| [[Image:Generic NCO.png|frame|Figure 1: Numerically controlled oscillator with optional quadrature output]]
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| When clocked, the phase accumulator (PA) creates a [[modulo operation|modulo]]-2<sup>N</sup> [[sawtooth wave]]form which is then converted by the phase-to-amplitude converter (PAC) to a sampled sinusoid, where N is the number of bits carried in the phase accumulator. N sets the NCO frequency resolution and is normally much larger than the number of bits defining the memory space of the PAC [[look-up table]]. If the PAC capacity is 2<sup>M</sup>, the PA output word must be truncated to M bits as shown in Figure 1. However, the truncated bits can be used for interpolation. The truncation of the phase output word does not affect the frequency accuracy but produces a time-varying periodic phase error which is a primary source of spurious products. Another spurious product generation mechanism is finite word length effects of the PAC output (amplitude) word.<ref name="kroupa">Kroupa,Venceslav F.,''Direct Digital Frequency Synthesizers'', IEEE Press, 1999, ISBN 0-7803-3438-8</ref>
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| The frequency accuracy relative to the clock frequency is limited only by the precision of the arithmetic used to compute the phase.<ref name="kroupa"/> NCOs are phase- and frequency-agile, and can be trivially modified to produce [[phase modulation|phase-modulated]] or [[frequency modulation|frequency-modulated]] by summation at the appropriate node, or provide [[quadrature phase|quadrature]] outputs as shown in the figure.
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| ==Phase accumulator==
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| <!-- linked from redirect [[Phase accumulator]] -->
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| A binary phase accumulator consists of an N-bit binary [[adder (electronics)|adder]] and a [[hardware register|register]] configured as shown in Figure 1.<ref name="Grzeg"/> Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size <math>\Delta F</math>, the integer value of the FCW.<ref name="ADI"/> In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle [[latency (engineering)|latency]] but allows the adder to operate at a higher clock rate.<ref name="latticeSC" />
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| [[Image:Phase Accum Graph.png|frame|Figure 2: Normalized phase accumulator output]]
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| The adder is designed to overflow when the sum of the [[absolute value]] of its operands exceeds its capacity (2<sup>N</sup>−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder <math>\phi _n</math>, called the residual, is stored in the register and the cycle repeats, starting this time from <math>\phi _n</math> (see figure 2).<ref name="Grzeg"/> Since a phase accumulator is a [[finite state machine]], eventually the residual at some sample K must return to the initial value <math>\phi _0</math>. The interval K is referred to as the grand repetition rate (GRR) given by
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| :<math>\mbox{GRR}=\frac{2^N}{\mbox{GCD}(\Delta F,2^N)}</math>
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| where GCD is the [[greatest common divisor]] function. The GRR represents the true periodicity for a given <math>\Delta F</math> which for a high resolution NCO can be very long.<ref name="Grzeg"/> Usually we are more interested in the ''operating frequency'' determined by the average overflow rate, given by<ref name="ADI">{{citation |url=http://www.analog.com/library/analogdialogue/archives/38-08/dds.html | |
| |title = All About Direct Digital Synthesis|publisher = Analog Devices, Inc.}}</ref>
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| :<math>F_{out} = \frac{\Delta F}{2^N}F_{clock} </math> (1)
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| The ''frequency resolution'', defined as the smallest possible incremental change in frequency, is given by<ref name="ADI"/>
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| :<math>F_{res} = \frac{F_{clock}}{2^N}</math> (2)
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| Equation (1) shows that the phase accumulator can be thought of as a programmable non-integer [[frequency divider]] of divide ratio <math>\Delta F/2^N</math>.<ref name= "kroupa"/>
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| ==Phase-to-amplitude converter==
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| The phase-amplitude converter creates the sample-domain waveform from the truncated phase output word received from the PA. The PAC can be a simple [[read only memory]] containing 2<sup>M</sup> contiguous samples of the desired output waveform which typically is a sinusoid. Often though, various tricks are employed to reduce the amount of memory required. This include various trigonometric expansions,<ref>{{Citation
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| |inventor-last =Miller
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| |inventor-first =Brian M.
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| |issue-date = October 14, 2008
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| |title =Numerically controlled oscillator and method of operation
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| |country-code =US
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| |patent-number =7437391
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| }}</ref> trigonometric approximations<ref name="Grzeg">{{Citation
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| |first = Grzegorz
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| |last = Popek
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| |first2 = Marian
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| |last2 = Kampik
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| |contribution = Low-Spur Numerically Controlled Oscillator Using Taylor Series Approximation
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| |contribution-url = http://mechatronika.polsl.pl/owd/pdf2009/030.pdf
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| |date = October 2009
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| |place = XI International PhD Workshop, Silesian University of Technology, Gliwice, Poland}}</ref> and methods which take advantage of the quadrature symmetry exhibited by sinusoids.<ref>{{Citation
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| |inventor-last =Mccallister
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| |inventor-first =Ronald D.
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| |inventor2-last =Shearer III
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| |inventor2-first =Daniel
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| |publication-date = 12/04/1984
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| |title =Numerically controlled oscillator using quadrant replication and function decomposition
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| |country-code =US
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| |patent-number = 4486846
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| }}</ref> Alternatively, the PAC may consist of [[random access memory]] which can be filled as desired to create an [[arbitrary waveform generator]].
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| ==Spurious products==
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| [[Spurious emission|Spurious]] products are the result of [[harmonic distortion|harmonic]] or non-harmonic [[distortion]] in the creation of the output waveform due to non-linear numerical effects in the signal processing chain. Only numerical errors are covered here. For other distortion mechanisms created in the [[digital-to-analog converter]] see the corresponding section in the [[Direct digital synthesizer|direct-digital synthesizer]] article.
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| ===Phase truncation spurs===
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| The number of phase accumulator bits of an NCO, N is usually between 24 and 64. If the PA output word were used directly to index the PAC look-up table an untenably high storage capacity in the ROM would be required. As such, the PA output word must be truncated to span a reasonable memory space. Truncation of the phase word cause [[phase modulation]] of the output sinusoid which introduces non-harmonic [[distortion]] in proportion to the number of bits truncated. The number of spurious products created by this distortion is given by:
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| :<math>n_W=\frac{2^W}{\mbox{GCD}(\Delta F,2^W)}-1</math> (3)
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| where W is the number of bits truncated.
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| In calculating the [[Spurious-free dynamic range]], we are interested in the spurious product with the largest amplitude relative to the carrier output level given by:
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| :<math>\zeta _{max}=2^{-M} \frac{\pi \mbox{GCD}(\Delta F,2^W)}{\sin \left( \pi \cdot 2^{-P}\mbox{GCD}(\Delta F,2^W) \right)}</math>
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| where P is word width of the DAC. For W >4,
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| :<math>\zeta _{max} \approx -6.02 \cdot P\;\mbox{dBc}.</math>
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| Another related spurious generation method is the slight modulation due to the GRR outlined above. The amplitude of these spurs is low for large N and their frequency is generally too low to be detectable but they may cause issues for some applications.<ref name="Grzeg"/>
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| ===Amplitude truncation spurs===
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| Another source of spurious products is the amplitude [[Quantization (signal processing)|quantization]] of the sampled waveform contained in the PAC look up table(s). If the number of DAC bits is P, the
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| AM spur level is approximately equal to −6.02 P − 1.76 [[dBc]].<ref name="intersil">{{cite web|title=The NCO as a Stable, Accurate Synthesizer|url=http://www.intersil.com/content/dam/Intersil/documents/tb31/tb318.pdf|publisher=Intersil Corporation|year=1998}}</ref>
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| ===Mitigation techniques===
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| Phase truncation spurs can be reduced substantially by the introduction of [[White noise|white gaussian noise]] prior to truncation. The so-called [[dither]] noise is summed into the lower W+1 bits of the PA output word to linearize the truncation operation. Often the improvement can be achieved without penalty because the DAC noise floor tends to dominate system performance. Amplitude truncation spurs can not be mitigated in this fashion. Introduction of noise into the static values held in the PAC ROMs would not eliminate the cyclicality of the trunction error terms and thus would not achieve the desired effect.<ref name="kroupa"/>
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| ==See also==
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| *[[Direct digital synthesizer]]
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| *[[Digitally controlled oscillator]]
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| *[[Digital-to-analog converter]]
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| ==References==
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| {{reflist|2}}
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| {{good article}}
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| {{DEFAULTSORT:Numerically Controlled Oscillator}}
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| [[Category:Digital signal processing]]
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| [[Category:Synthesizers]]
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| [[Category:Oscillators]]
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| [[Category:Digital electronics]]
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