en>Addbot: Bot: Migrating 1 interwiki links, now provided by Wikidata on d:q1780715

2013-03-16T06:09:06Z

Bot: Migrating 1 interwiki links, now provided by Wikidata on d:q1780715

← Older revision		Revision as of 08:09, 16 March 2013
Line 1:		Line 1:
	~~Her name~~ is ~~Felicidad Ahmad~~. ~~To play handball~~ is the ~~factor she loves most~~ of ~~all~~. ~~Some time ago I chose~~ to ~~reside~~ in ~~Arizona but I require~~ to ~~transfer for my family members~~. ~~Interviewing is what she does but quickly she~~'ll be ~~on her own~~.<br><br>~~my web site; [http~~://~~Www~~.~~Teamprefire~~.de/~~index~~.~~php?mod~~=~~users&action~~=~~view&id~~=~~14578 Www~~.~~Teamprefire.de~~]		'''Logic optimization''', a part of [[logic synthesis]], is the process of finding an equivalent representation of the specified [[logic circuit]] under one or more specified constraints. Generally the circuit is constrained to minimum chip area meeting a prespecified delay.

			==Introduction==

			With the advent of [[logic synthesis]], one of the biggest challenges faced by the [[Electronic design automation]](EDA) industry was to find the best [[netlist]] representation of the given design description. While [[two-level logic optimization]] had long existed in the form of the [[Quine–McCluskey algorithm]], later followed by the [[Espresso heuristic logic minimizer]], the rapidly improving chip densities, and the wide adoption of [[Hardware description language\|HDLs]] for circuit description, formalized the logic optimization domain as it exists today.

			Today, logic optimization is divided into various categories based on two criteria:

			'''Based on circuit representation'''
			* Two-level logic optimization
			* Multi-level logic optimization'''

			'''Based on circuit characteristics '''
			* Sequential logic optimization
			* Combinational logic optimization

			While a [[two-level circuit representation]] of circuits strictly refers to the flattened view of the circuit in terms of SOPs ([[Canonical form (Boolean algebra)\|sum-of-products]]) — which is more applicable to a [[Programmable logic array\|PLA]] implementation of the design{{Clarify\|date=February 2010}} — a [[multi-level representation]] is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs ([[Canonical form (Boolean algebra)\|product-of-sums]]), factored form etc. Logic optimization algorithms generally work either on the structural (SOPs, factored form) or functional (BDDs, ADDs) representation of the circuit.{{Clarify\|date=February 2010}}

			==Two-level versus multi-level representations==

			If we have two functions ''F''<sub>1</sub> and ''F''<sub>2</sub>:

			: <math>F_1 = AB + AC + AD,\,</math>

			: <math>F_2 = A'B + A'C + A'E.\,</math>

			The above 2-level representation takes six product terms and 24 transistors in CMOS Rep.{{Why\|date=February 2010}}

			A functionally equivalent representation in multilevel can be:

			: ''P'' = ''B'' + ''C''.

			: ''F''<sub>1</sub> = ''AP'' + ''AD''.

			: ''F''<sub>2</sub> = ''A<nowiki>'</nowiki>P'' + ''A<nowiki>'</nowiki>E''.

			While the number of levels here is 3, the total number of product terms and literals reduce {{Quantify\|date=February 2010}} because of the sharing of the term B + C.

			Similarly, we distinguish between [[Sequential logic\|sequential]] and [[Combinational logic\|combinational circuits]], whose behavior can be described in terms of [[finite-state machine]] state tables/diagrams or by Boolean functions and relations respectively.{{Clarify\|date=February 2010}}

			== See also ==
			*[[Binary decision diagram]]
			*[[Circuit minimization]]

			== References ==
			*''Synthesis and Optimization of Digital Circuits'', by Giovanni De Micheli, ISBN 0-07-016333-2.

			[[Category:Electronic engineering]]
			[[Category:Electronic design]]
			[[Category:Digital electronics]]
			[[Category:Electronic design automation]]
			[[Category:Electronics optimization]]

en>Cydebot: Robot - Speedily moving category Convergence to :Category:Convergence (mathematics) per CFDS.

2011-11-18T22:57:57Z

Robot - Speedily moving category Convergence to Category:Convergence (mathematics) per CFDS.

New page

Her name is Felicidad Ahmad. To play handball is the factor she loves most of all. Some time ago I chose to reside in Arizona but I require to transfer for my family members. Interviewing is what she does but quickly she'll be on her own.<br><br>my web site; [http://Www.Teamprefire.de/index.php?mod=users&action=view&id=14578 Www.Teamprefire.de]

Compact convergence - Revision history

en>Addbot: Bot: Migrating 1 interwiki links, now provided by Wikidata on d:q1780715

en>Cydebot: Robot - Speedily moving category Convergence to :Category:Convergence (mathematics) per CFDS.